A Processing Element for an Analogue SIMD Vision Chip

− This paper describes an analogue processing element (APE) suitable for high-density image sensor/processor array integrated circuits. The design tradeoffs between area, power consumption, speed and accuracy are discussed and the architecture of the APE is presented. The design follows a switched-current “analogue microprocessor” approach while the implementation of arithmetic operations is simplified by introducing a registerbased current division method. The circuit has been implemented in a 0.35μm single-poly 3-metal layer CMOS technology. The APE measures below 50μm×50μm, operates with a 1 MHz clock and consumes less than 12μW of power (simulation results).